1. Field of the Invention
The present invention relates to a method of plasma processing a sample such as a semiconductor integrated circuit and, particularly, to a dry etching method suitable for the treatment of an insulating film material having a low dielectric constant.
2. Related Background Art
Semiconductor integrated devices have a relatively larger electrostatic capacity between adjacent wirings in a wiring portion as the design rule is becoming narrower. When a conventional silicon oxide film is used as an insulating material between wirings, the benefit of increasing the speed of a transistor obtained by reducing the design rule cannot be obtained. Therefore, a material having a low dielectric constant (k value) is now used as an insulating material between wirings.
Since the above material is mainly used in combination with the copper of a wiring material and formed with means called “dual damascene”, the step of etching the insulating material is necessary. This forming step using the dual damascene includes the substep of obtaining a predetermined form for a sample having a hole formed in the previous step by transferring a groove form to a porous insulating film using a hard mask. This technology is disclosed by Japanese Patent Laid-open No. H9(1997)-115878, for example.
Heretofore, when a process having a small margin due to a reduction in design rule is used, the reproduction stability of a treatment has been obtained by washing and cleaning a chamber periodically using a quality control technique. Also, the method of controlling the process by monitoring the state of the process has also been employed.
As the method of controlling the process by monitoring the state of the process is known a method in which etching is stopped by monitoring reflection interference light from the treated wafer as disclosed in U.S. Pat. No. 5,658,418.
However, process conditions required for a normal treatment are becoming more strict along with the narrowing design rule and further due to a specific phenomenon caused by porosity shown below. Materials having a low dielectric constant (k value) are now widely used due to a reduction in design rule and also materials having pores introduced therein called “porous insulating film” are used to further reduce the dielectric constant.
Further, a mask material is removed by using another vacuum vessel or other device in the same apparatus after the end of etching in the prior art. For example, Japanese Patent Laid-open No. 2000-352827 discloses a technology for removing the etching residue or a curing layer on the surface of a resist by a wet process.
Since a process having low tolerance and strict conditions is easily affected by the surface state of a chamber and the etched area of the treated wafer, the greatest care must be taken of the control of treatment reproducibility.
Particularly, in the etching of a porous insulating film, the influence of the geometrical structure of a pore appears though the structure is fine. The case where there is a pore and the case where there is no pore are compared conceptually with reference to FIGS. 12A and 12B when the pore is seen microscopically. When there is no pore in the material, as shown in FIG. 12A, the angle α between an ion having a certain incident angle and the etched surface 122 of a material 120 is the same, for example, 90° at different positions S1 and S2 on the horizontal plane as a matter of course. On the other hand, when there is a pore 124 in the material 120, as shown in FIG. 12B, the angle α between the ion and the etched surface 122 at a position S1 may differ from the angle α at a different position S2 on the horizontal plane. Meanwhile, ions having different incident angles may differ in etching rate. Thereby, the influence of the pore appears in the material having the pore 124 in an exaggerated manner.
Seeing the scale of a pattern for processing this, as shown in FIG. 13, when a groove is to be formed in a porous insulating film 120 on a base film 134 by etching using a hard mask 130, the surface having a groove form is roughened 132 during etching and grows. Finally, a plurality of residues 140 as shown in FIG. 14 remain in the bottom of the etched groove.
The residues 140 cause an embedding failure during the subsequent step of metal deposition and cannot be removed by cleaning. Therefore, they must be completely removed in the etching step. It is possible to reduce the amount of the residues to a certain extent by increasing the over-etching time. However, the shoulder portion of the hard mask is easily chipped off by increasing the over-etching time, thereby causing a reduction in yield such as a short-circuit between wirings. An increase in over-etching time also causes the etching of the base film 134 and a dimensional error. Therefore, countermeasures must be taken in the etching step.
To achieve a treatment without the residues and the high-accuracy transfer of a pattern at the same time, neutral deposition and etching radicals are well balanced. However, the external controllability of neutral radicals does not reach a required level and a quality control technique must be introduced. That is, a method of actually processing a test wafer at a cycle at which safety can be expected by statistically acquiring information on influencing changes and confirming the process is necessary.
However, control frequency and the number of wafers to be confirmed are increased by a further reduction in tolerance due to a reduction in design rule, thereby boosting cost.